-- 32 bit version register file
-- evillase

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity registerFile is
	port
	(
		-- Write data input port
		wdat		:	in	std_logic_vector (31 downto 0);
		-- Select which register to write
		wsel		:	in	std_logic_vector (4 downto 0);
		-- Write Enable for entire register file
		wen			:	in	std_logic;
		-- clock, positive edge triggered
		clk			:	in	std_logic;
		-- REMEMBER: nReset-> '0' = RESET, '1' = RUN
		nReset	:	in	std_logic;
		-- Select which register to read on rdat1 
		rsel1		:	in	std_logic_vector (4 downto 0);
		-- Select which register to read on rdat2
		rsel2		:	in	std_logic_vector (4 downto 0);
		-- read port 1
		rdat1		:	out	std_logic_vector (31 downto 0);
		-- read port 2
		rdat2		:	out	std_logic_vector (31 downto 0)
		);
end registerFile;

architecture regfile_arch of registerFile is

	constant BAD1	:	std_logic_vector		:= x"BAD1BAD1";

	type REGISTER32 is array (1 to 31) of std_logic_vector(31 downto 0);
	signal reg	:	REGISTER32;				-- registers as an array
	signal i	:	integer;
  -- enable lines... use en(x) to select
  -- individual lines for each register
	signal en		:	std_logic_vector(31 downto 0)   := x"00000000";
	component lpm_decode
	generic (
		lpm_decodes		: natural;
		lpm_type		: string;
		lpm_width		: natural
	);
	port (
			eq	: OUT STD_LOGIC_VECTOR (lpm_decodes-1 DOWNTO 0);
			data	: IN STD_LOGIC_VECTOR (4 DOWNTO 0)
	);
	end component;
	
begin

	-- registers process
   registers : process (clk, nReset, en)
	begin
		-- one register if statement
		if (nReset = '0') then
				-- Reset here
				for i in 1 to 31 loop
					reg(i) <= x"00000000";
				end loop;
		elsif (rising_edge(clk)) then
				-- Set register here				
				if (wen = '1') then
					for i in 1 to 31 loop
					   if (conv_integer(wsel) = i) then
   					      reg(i) <= wdat;
   					   end if;
         			   end loop;
				end if;
		end if;
	end process;

	--decoder for assigning en:
	--en <= x"00000000";

	
	--rsel muxes:
	with rsel1 select	
	rdat1 <= x"00000000" when "00000",
		reg(conv_integer(rsel1)) when others;
	
	with rsel2 select
	rdat2 <= x"00000000" when "00000",
		reg(conv_integer(rsel2)) when others;
	
end regfile_arch;
